The present invention concerns a bus controller which dynamically changes timing for data transfers on the bus.
In a computer system, peripheral devices are generally connected to the computer system via a peripheral bus. A computer system may use a separate peripheral processor to communicate with peripheral devices on the peripheral bus.
A bus clock signal is generated to control the speed of data transfer on the bus. For example, a peripheral processor may generate the bus clock signal. However, not all peripheral devices are able to transfer data at the same rate. Therefore, to insure proper operation of the computer system, the peripheral processor must transfer data at a rate acceptable to all peripheral devices on the bus.